Next generation AMD Epyc processor, the Venice Code name is the first HPC product to use TSMC Node N2 – But I wonder if Apple was first


  • AMD shows its first Die CPU of Venice Class of Class 2 Nm using TSMC node N2
  • Venice, built on Zen 6, targets high performance IT workloads
  • AMD and TSMC hope to deepen their collaboration for future innovations

AMD announced that it had successfully produced the first class 2 NM silicon for its new generation Epyc processor, the code name “Venice” which should be launched in 2026 as part of the EPYC range of 6th generation of AMD.

The Core Complex Die (CCD) is the first high performance computer product to be recorded and high using advanced N2 Advanced TSMC technology.

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