- APU MI400 of AMD in 2026, increasing AI, HPC and calculation of efficiency
- The new design includes two aids with eight XCD, double the density of the MI300
- Multimedia Io Die unloads io tasks and can integrate Xilinx FPGA Tech
The MI400 APU instinct for AMD should arrive in 2026 – designed for AI, automatic learning and HPC workloads, the MI400 will be based on modular architecture based on the Red Team Chiplet and should increase Calculation density, energy efficiency and scalability.
He can also play a role in future SuperCalculculua projects, including a possible successor from El Capitan, but so far AMD has only confirmed that the MI400 will use the “Next” DNA.
However, ut a patch updating the header of the API for MES (Microengine Scheduler) V12, spotted by Coelacanth’s dream (and reported by Video), provides an overview of its chiplet configuration.
According to the fix, the MI400 will have two matrices to interpose active (AID), each containing four accelerated calculation matrices (XCD), for a total of eight XCD. This doubles the XCD number per help compared to the MI300. By integrating more calculation calculations in fewer interposers, AMD could reduce latency and improve efficiency while increasing data flow, which is essential for AI and HPC workloads.
However, as Coelacanth’s dream Underlines: “If the MI400 follows a similar CPU complex matrix (CCD) and aid partitioning as MI300, where certain AIDS are dedicated to CPUs rather than accelerators, then the maximum number of XCDS in certain configurations could be Limited to four, potentially potentially reduce the XCD number compared to the APU Mi300A. »»
An intriguing addition to the MI400 is the Die io Multimedia (MID), which separates the multimedia engine from AIDS. MID will likely manage memory controllers, multimedia engines and interface logic, allowing calculation matrices to focus on treatment tasks. The fixes suggest a support for up to two mediums, probably assigning one by aid.
This new component could be the first AMD integration of VPGA toal / Xilinx technology in its Accelerator range. AMD announced in 2022 that it planned to incorporate the AI inference engine supplied by FPGA from Xilinx in its CPU portfolio. It could also be an acceleration card of the Alveo data center.
The fixes also refer to a registry remapping table (RRMT), allowing the firmware to direct registration transactions to specific aids, XCD or mediums.
AMD has not yet published official rendering or specifications for the MI400 series, but with the accelerator which should be launched in 2026, after the arrival of the Instinct MI350 series (built on the architecture DNC 4) later This year, more details will emerge, hope, will emerge, let’s hope it soon.
