- SK Hynix split-cell 5-bit flash memory increases SSD density without significantly reducing production complexity
- RAID-0-like parallelism in split-cell NAND significantly increases read speed
- Each half-cell reduces voltage stress, extending flash endurance by five bits
The NAND flash industry continues to look for ways to increase storage density as demand increases for data centers, consumer devices and AI tools.
Conventional scaling via additional 3D NAND layers has become increasingly complex, expensive, and difficult to manufacture consistently.
While four-bit QLC flash is already in commercial production, the move to five-bit PLC flash has remained impractical due to reliability and endurance issues related to voltage sensing limits.
How Split-Cell Flash Changes the Equation
SK Hynix introduced a different approach known as multi-site cellular technology. Instead of forcing a single NAND cell to maintain all 32 voltage states, the design splits the cell into two independent half-cells.
Each half stores six voltage states, which combine to represent a five-bit value. This design reduces voltage footprint while maintaining overall bit density.
The two half-cells operate in parallel as a single logical unit, resembling how RAID-0 strips data across hard drives to increase throughput.
In this case, voltage states combine upon access rather than being distributed across separate devices.
The physical shape of the cell is elliptical rather than circular, which leaves room for an insulating wall between the halves and separate bitline connections.
SK Hynix claims that wider voltage gaps in each half-cell reduce electron leakage and shorten programming time.
Both halves are read simultaneously, which the company says provides faster read speeds compared to conventional PLC designs.
This method also improves endurance, as lower voltage reduces cell wear.
SK Hynix demonstrated functional wafers at the IEDM 2025 conference, signaling that the concept extends beyond simulation.
The split-cell approach requires additional steps in the semiconductor process, including cell division and gap filling, which increases cost and complexity.
While SK Hynix evaluates manufacturability, other flash makers, including Samsung, Micron, Kioxia and Sandisk, are expected to explore similar ideas.
The concept doesn’t promise cheaper SSDs, only denser SSDs, and it doesn’t eliminate the role of hard drives in high-capacity storage.
If manufacturers can produce multi-site cells at scale, CPL flash could finally become viable without the serious drawbacks seen in earlier designs.
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