- Apollo 2 Switch supports the Gen 6.2 and CXL 3.1 inside a single hybrid chip
- Xconn wants to redefine the bandwidth limits, but the results of the real world remain completely not tested
- Intel and Xconn collaborate to test complete compatibility in PCIE -based ecosystems
XCONN Technologies is preparing to demonstrate what he describes as a solution of PCIe Gen 6.2 and CXL 3.1 entirely integrated during the next Future of Memory and Storage event (FMS25).
The company positions the launch as a critical step towards satisfying the performance needs of the workloads of the AI and the data center.
However, as with any technological demo at an early stage, the scalability and reliability of the real world are always open questions.
Hybrid switch with theoretical flexibility
The Apollo 2 switch of the company will be at the heart of this unveiling – marketed as the first hybrid switch of the industry to support PCIe Gen 6.2 and CXL 3.1 In a single chip, it is supposed to simplify interconnection conceptions and improve scalability.
“XCONN is delighted to provide PCIe Gen 6.2 and CXL 3.1 market switches, with samples now available,” said Gerry Fan, CEO of Xconn Technologies.
“While industry is accelerating towards more -centered and high performance intensity architectures, our commitment is to allow the best customers in its category.”
These advantages aim to reduce complexity in data centers while allowing wider architectural flexibility.
Although technically promising, the real advantage of such integration will depend on performance results in the context of production quality workloads.
The collaboration of Xconn with Intel is also positioned as a major development, because according to Ronak Singhal, senior colleague of Intel, the partnership will help to guarantee that software and material components interact gently, offering “robust end -to -end solutions”.
Companies expect this effort to promote an interoperable environment for PCIE and CXL technologies.
However, experiences in the industry suggest that successful validation often takes time and more than one demonstration cycle.
The coming demo will present a low -band switching switch to low latency, highlighting the preparation of the infrastructure for applications such as the formation of the AI / ML model, Cloud Computing and the composable infrastructure.
The XCONN stand would have a configuration entirely based on standards, but until the benchmarks are published, it is difficult to determine the improvement of users that users can expect compared to existing PCIE Gen 5 deployments.
XCONN also joined forces with Scaleflux to improve CXL 3.1 interoperability for AI and cloud infrastructure.
Although this indicates momentum, this does not confirm to what extent the solution fits into the types of workloads which currently underline the architectures of today.
The implications for high -speed storage are significant if the technology offers.
With growing demand for the largest SSD capacities and the fastest SSD performance, PCIe Gen 6 could support faster data transfers between storage devices and processing units.
However, these theoretical gains must be tempered with skepticism until the field data confirm the impact.
XCONN’s demo may well mark the start of the next chapter of the AI equipment. But for the moment, there is still an overview, not a point of evidence.
Via TechPowerUP
