XCENA MX1 Calculation MXNA combines thousands of RISC-V cores with CXL 3.2 and SSD


  • Xcena has introduced MX1 calculation memory with thousands of RISC-V cores at FMS 2025
  • MX1 provides almost processing of data for the processor’s general costs and activating sustained expansion of the SSD on a petactive scale
  • The product roadmap includes MX1P this year and MX1 in 2026 supporting CXL 3.2

During the recent FMS 2025 event (formerly Flash Memory Summit, but now called Future of Memory and Storage to better adapt to its enlarged development), the South Korean startup Xcena took the wraps of its first product, MX1 Computational Memory.

MX1 is built on the PCIe Gen6 standard and the Calpeput Express Link 3.2 standard. By putting the calculation directly next to DRAM, the chip is able to reduce the general costs of the movement of data between processors and memory.

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