- Marvell Structera X 2404 enables DDR4 reuse without purchasing new DRAM
- Twelve DIMMs per controller provide 1.5 TB of physical memory capacity
- Memory compression effectively doubles usable capacity using LZ4 at line rate
Hyperscalers, under pressure from rising memory prices, may turn to decommissioned DDR4 modules as a practical resource.
The Marvell Structera X 2404 is a CXL-based memory expander designed to make large-scale DDR4 module reuse viable.
When operators install 128 GB units from outdated systems, the controller provides up to 1.5 TB of physical capacity without the need for new DRAM.
Structera X 2404 deployment diagram
The Structera X 2404 fits into standard data center server racks as a PCIe attached device rather than a traditional DIMM, so it functions as an external memory resource.
It supports four DDR4 channels and allows three DIMMs per channel, creating a total of twelve modules connected to a single controller.
This approach appeals to hyperscalers due to the large quantities of older modules stored from previous upgrade cycles.
This also reduces manufacturing requirements because only the controller, board, and cable require production, not the DRAM itself.
The DDR4 model focuses on cost, but some operators need higher performance than older modules can offer.
The Structera X 2504 serves these environments and uses four-channel DDR5 RAM.
It connects via CXL 2.0 over PCIe Gen5 and offers more bandwidth because it bypasses the processor’s memory channels.
This design appeals to deployments that require faster throughput while seeking expansion beyond the limitations of the processor’s DDR5 DIMM slots.
The most notable feature of both devices is memory compression, which changes the way capacity is provisioned and priced.
Marvell uses the LZ4 at line rate and reports ratios between 1.8x and 2x during normal operation. This means that a capacity of 1.5 TB can grow to 3 TB.
This approach allows hyperscalers to treat reused DDR4 as a larger, cheaper pool than its physical size suggests.
This also reduces pressure on DDR5 supply chains because systems can rely on compressed expansion rather than purchasing additional modules.
That said, latency remains the main concern as independent testing under real workloads has not yet taken place.
CXL already introduces additional delay, and compression adds more uncertainty when memory access becomes unpredictable.
Without third-party random read latency testing, it remains unclear whether these devices perform well in dispersed access patterns.
Random reads affect many production systems, and slow responses can wipe out the benefits of additional capacity.
This uncertainty represents the greatest technical risk, because latency determines whether the extension behaves like real memory or one tier slower.
Via ServeTheHome
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