- IBM pushes transistor density below the dreaded nanometer barrier
- NanoStack abandons flat die layouts in favor of vertical stacking of transistors
- Prototype delivered 50% more performance during IBM lab testing
IBM has unveiled what it describes as the world’s first sub-1nm chip technology, carrying nearly 100 billion transistors on an area the size of a fingernail.
This advancement centers around a new 3D NanoStack architecture that takes transistor scaling to the 0.7 nm or 7 angstrom era.
As a reminder, today’s most advanced commercial chips are typically around the 2nm mark, which represents a substantial jump in density.
Building Up to Keep Moore’s Law Alive
The semiconductor industry has spent decades packing more transistors onto smaller and smaller pieces of silicon to improve computing performance.
This process has become increasingly difficult as transistor dimensions approach the scale of just a few atoms in modern processors.
IBM’s approach avoids additional horizontal compression by stacking transistor layers vertically via a three-dimensional nanosheet architecture.
The design contains nearly twice the transistor density of IBM’s 2nm chip technology introduced in 2021.
According to the company, the architecture also offers approximately 40% greater SRAM scalability to support increasingly demanding AI workloads.
This vertical method allows engineers to separate N- and P-type transistors into separate layers, which IBM says allows for independent material optimization for each.
compared it to building a large apartment building rather than houses in a city.
“IBM’s NanoStack is like proposing a 100-story skyscraper,” said Professor Alan Woodward, a computer scientist at the University of Surrey.
Using this analogy, IBM’s closest competitors, like Intel and Samsung, are located somewhere in a 30-50 story building, far away from IBM.
In testing, the company reported a 50% performance improvement and 70% higher power efficiency compared to its existing 2nm chips, as well as a 40% gain in on-chip memory scaling.
Despite the cited performance improvements, the technology remains years away from commercial use, with IBM estimating that production could begin within five years at the earliest.
“With our new NanoStack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver significantly greater power and energy efficiency,” said Jay Gambetta, IBM research director and IBM Fellow.
The trade-offs behind density gains
Vertical stacking introduces complications primarily related to heat dissipation, because transistors generate heat that becomes more difficult to manage when stacked on top of each other.
This same tight spacing also raises the stakes when it comes to wafer alignment, since the layers must be bonded with extreme precision to avoid malfunction.
Researchers recognize that when gaps between layers become too thin, transistors may not turn off properly, compromising the density gains that NanoStack is supposed to offer.
These technical compromises are symptoms of a deeper problem facing the entire chip industry.
For decades, manufacturers have relied on Moore’s Law, which states that the number of transistors doubles approximately every two years.
But that pace has become increasingly difficult to maintain as designs approach the physical limits of individual atoms.
Whether NanoStack will actually extend this trajectory for another decade, as IBM predicts, depends on whether these unsolved manufacturing challenges can be solved at scale.
That’s part of the reason IBM has brought on partners like ASML, Lam Research, and Tokyo Electron, signaling an industry-wide effort behind this push toward angstrom-level scaling.
Despite this, similar bold claims accompanied IBM’s 2nm chip unveiling in 2021, but turning the lab’s success into mass production historically takes longer than initial announcements.
Via IBM
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