- Huawei offers Tau’s scaling law as an alternative to Moore’s law scaling
- LogicFolding architecture reduces signal delay with vertically stacked solid-state circuit designs
- Shrinkage of traditional transistors faces growing physical and economic limitations in the semiconductor industry
For more than five decades, the semiconductor industry has relied on a simple and powerful prediction, Moore’s Law, that transistors on a chip double approximately every two years, now faces serious physical and economic obstacles.
The global industry faces slowing geometric evolution and a steady erosion of cost per transistor advantages.
This common challenge has forced all major players to seek a new path forward, and at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo proposed an alternative framework called the Tau (τ) scaling law.
A new guiding principle from Shanghai
According to Huawei, its peers and colleagues have already dubbed this approach “Her’s Law” in recognition of its leadership.
Rather than focusing on reducing transistor dimensions, this principle prioritizes reducing signal propagation delay.
Huawei believes that compressing the time constant τ can lead to continuous evolution of semiconductors and electronic systems.
The main technological advance enabling this new law is a technique called LogicFolding.
Traditional chip design presents all electronic components in a flat 2D grid that limits circuit proximity – and LogicFolding breaks the physical limitations of conventional circuit layouts by dramatically shortening critical path wiring.
It reduces the resistive and capacitive loading that normally slows signal propagation between transistors.
The result is a systematic compression of the time constant τ simultaneously at the circuit and chip level.
Huawei has abandoned traditional 2D chip design in favor of a layered 3D architecture.
Think of this transition as going from a one-story home to a multi-story building with efficient elevators. Huawei can now stack multiple planar circuits vertically, creating room for more transistors while placing core components closer together.
Shorter transmission distances between circuits directly improve frequency and overall performance.
Practical results and future ambitions
Huawei claims to have already mass-produced 381 chips using this new scaling law across various industries.
The upcoming Kirin chips, scheduled to launch in fall 2026, will be the first to adopt the LogicFolding architecture.
By 2031, the company expects its high-end designs to achieve transistor density equivalent to 14 Å or 1.4 nm processes.
“We believe that openness and collaboration are essential for continued progress in the semiconductor industry,” said He Tingbo.
“No single company can find all the answers throughout the evolution of semiconductors.”
Huawei has a vested interest in projecting confidence, given its current restrictions on accessing TSMC’s advanced manufacturing tools or purchasing Nvidia’s latest AI chips.
Whether the scaling law τ can actually surpass Moore’s law in the next decade remains an open question.
Competing companies will likely treat this announcement with measured skepticism until the actual hardware reaches neutral testing labs.
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